The bus protocol in high-performance, highly pipelined bus architecture may allow for a high degree of overlapped activity. For instance, arbitration, transfer, decoding and transfer acknowledge may be 4 stages of request handling that may be underway for 4 distinct requests at the same moment. Thus, First-In, First-Out (FIFO) style buffering which will, under certain conditions, fill up, either causing a transaction to wait for the FIFO to become available or send a BUSY response to the requesting device, asking it to try again at a later time. It is not desirable to have a device occupy the bus while waiting for another device to make its buffers available since this makes the bus bandwidth unavailable for other transfers, causing valuable bus bandwidth to be needlessly tied up. This problem becomes more severe in the case of a multiprocessor system sharing a single bus resource, since the bus may become the system bottleneck. Moreover, in certain implementations a slow device on the bus can magnify this problem even further, since the whole system will start to run at the speed of this slow device.
Moreover, if a device is in the process of performing multiple writes across the bus, it must either wait for a previous write to be acknowledged as accepted before sending another write, or it must obey some protocol that will insure that write order is preserved. Waiting for a previous write to be acknowledged before issuing another write is lower performance than sending another write as soon as possible. However, in some pipelined system bus protocols, sending another data write will likely not preserve write order of data, causing processing errors.
Therefore, it is important to preserve write order so that information may be passed in control blocks from process to process, processor to processor, and I/0 system to processors. Control blocks are normally formulated by assembling the information into some predetermined format and then setting some ready flag or setting up some queue pointer. However, if a write to a ready flag manages to occur prior to a write setting up some information in the control block, the receiving process will get a corrupted message.
SUMMARY OF THE INVENTION
The computer system having write order preservation for the bus data transfers according to the present invention requires a minimum of one unused cycle between successive writes by a given device, where "unused" means unused by that particular device for a write operation, and a REJECT signal to indicate to all devices that the command that they just received is invalid.
The protocol, according to the present invention, has been applied to a specific bus architecture; however, the concept is extendible to other architectures. The bus is a synchronous bus that is capable of initiating a read or a write operation in every bus cycle. Bus arbitration may also occur in a single cycle, which may be overlapped with other transfers, so that it is quite Possible that a write operation could be initiated in every cycle. Every bus transaction is accompanied by an acknowledgment from the receivin9 device in the second cycle after the transaction bus cycle. The acknowledgment cycles are completely overlapped with other transactions so they do not affect bus bandwidth.